This invention relates to digital filters and more particularly to digital filters used in communication systems.
In many wireless communication systems, such as those compliant with technical specifications organized by the Third Generation Partnership Project (3GPP), gaussian minimum shift keying (GMSK) modulation is used for impressing digital data onto a radio frequency (RF) carrier signal. The modulated carrier signal is then transmitted by a communication device, such as a mobile telephone, computer, network base station, etc.
A frequency synthesizer that generates the RF carrier signal in the transmitter (TX) of the communication device can be configured for direct GMSK modulation. Direct synthesizer modulation can give better RF signal-to-noise performance than a traditional quadrature (in-phase/quadrature-phase, or I/O) RF modulator. The frequency synthesizer in many communication devices is a phase-locked loop (PLL).
FIG. 1 is a block diagram of a portion 100 of a transmitter of a communication device that implements single-point modulation. Data bits to be modulated onto the carrier signal are passed through a Gaussian pulse-shaping filter 102 and a pre-emphasis filter 104 to a summer 106 that also receives a suitable frequency control signal from a controller 108. The output of the summer 106 is a control signal for a PLL 110 that includes a reference frequency generator 112, a phase detector 114, a loop filter 116, a voltage-controlled oscillator (VCO) 118, and a fractional-N divider 120. The PLL 110 generates a GMSK-modulated RF carrier signal that can be amplified by a power amplifier and transmitted through a suitable antenna. The power amplifier and antenna are not shown in FIG. 1 for clarity.
The Gaussian pulse-shaping filter 102 can conveniently be a digital filter, and the pre-emphasis can be implemented either by modifying the taps (i.e., filter coefficients) of the Gaussian filter 102 or by using a separate pre-emphasis filter 104 as depicted in FIG. 1. The Gaussian filter 102 typically has a Finite Impulse Response (FIR) topology, and the pre-emphasis filter 104 can have an FIR or Infinite Impulse Response (IIR) topology.
As seen in FIG. 1, the modulation is applied at a single point, i.e., the control input of the fractional-N synthesizer frequency divider 120, which receives the output of the summer 106 as a control word. The divided VCO frequency is compared to the reference frequency, and since the modulation affects the division ratio, the modulation is applied to the VCO, which provides the modulated signal generated by the PLL 110.
A problem arises in that a PLL can have a frequency response, or modulation bandwidth (BW), that is too low for the GMSK modulation specified for the particular communication system. The PLL 110 has a low-pass frequency response for the divider 120/summer 106 modulation point, but a role of the pre-emphasis filter 104 is to overcome the PLL BW limitation. The pre-emphasis filter 104 has a high-pass frequency response that is matched to compensate the PLL's low-pass frequency response. The cascade of the pre-emphasis filter 104 and PLL 110 can have a frequency response that is wide enough for the desired GMSK signal.
U.S. Pat. No. 7,912,145 shows a basic structure of a fractional-N synthesizer, with an adaptive pre-emphasis filter that is controlled by an incoming signal W and comparing with the feedback from a VCO control voltage. The pre-emphasis filter's transfer function, i.e., its frequency response, i.e., is changed based on the input signal and feedback signal difference.
Another way to handle the sometimes limited bandwidth of a PLL-based direct-modulated transmitter is to use two-point modulation. FIG. 2 is a block diagram of a portion 200 of a transmitter of a communication device that implements two-point modulation. It will be understood that there is typically no need for pre-emphasis in two-point modulation. Thus, FIG. 2 shows many of the same components as FIG. 1 that are identified by the same reference numerals, but the arrangement in FIG. 2 omits the pre-emphasis filter 104 and changes the PLL 210. Instead of a single-point modulation at the summer 106, FIG. 2 shows the modulation is applied at two points: the control input of the fractional-N divider 120 generated by the summer 106 as in FIG. 1, and the input of the VCO 118 that is generated by a second summer 222. From the point of view of the modulated output signal, the PLL 210 has a low-pass frequency response for the divider 120/summer 106 modulation point and a high-pass frequency response for the VCO 118/summer 222 modulation point. The two modulation points make it possible to widen the modulation BW with suitably scaled signal levels at the modulation points.
A FIR filter can require a large number of taps in order to get the desired transfer function, or frequency response, which means a large size in an implementation on an integrated circuit, but a FIR filter has no signal level offset problem. An IIR filter is compact in size, but it has an offset problem when it is implemented using fixed-point arithmetic. Signal level offsets are generated when there are long sequences of successive zeros or ones in the stream of modulation data bits, or symbols, i.e., when an IIR filter has an input signal value that is constant for a long-enough period of time. The filter offset is seen as a frequency deviation error of the modulated RF signal, and ultimately as increased root-mean-square (RMS) phase error.
U.S. Pat. No. 7,051,127 selectively pre-emphasizes data, and adds a parallel driver, which is used during the initial portion of a sequence of same symbols/data to compensate circuit level errors in interfaces between integrated circuits (ICs).